The invention relates generally to voltage regulators and, more particularly, to a threshold voltage adjustment scheme for increased output swing.
Certain circuits require an output stage that can go very close to the upper rail voltage while maintaining low impedance. The source follower is an obvious choice to meet the low impedance requirement. Ideally, a natural NMOS device would be the best choice for these kinds of output stages in order to maximize the output swing. But when a particular process does not contain natural devices, designers are only left with the next best choice: low-Vt MOS devices. When used in an output stage, these low-Vt, devices can pose a significant problem in meeting the output swing requirements at some process corners.
An example of a circuit that needs a low input and high output swing output stage is a low drop-out (LDO) voltage regulator with an NMOS buffer driving the gate of a PMOS pass device. One such PMOS LDO 100 is illustrated in FIG. 1. Voltage 105 (V2) is supplied to the non-inverting input of amplifier 110. Amplifier 110 receives operational power from the upper rail voltage at node 125 and also receives, at its inverting input, a voltage produced at node 130 between series-connected resistors 132 (R1) and 134 (R2). R1132 and R2134 are collectively referenced as feedback resistors 150. Amplifier 110 has an output coupled to the gate of NMOS source follower 115. Both the source and backgate of NMOS source follower 115 are tied to node 117. Node 117 is also tied to the gate of PMOS pass device 120. The drain of NMOS source follower 115 and both the source and backgate of PMOS pass device 120 are tied to the upper rail voltage at node 125. Feedback resistors 150 couple the drain of PMOS pass device 120 at node 135 to the ground supply voltage source. Capacitor 140 (C1) is tied from node 135 to ground. Low impedance is needed for the compensation of LDO 100. PMOS pass device 120 is a very large transistor that will provide current 160 (I1) to a load connected to the output of LDO 100 at node 135. C1140 also at node 135, on the order of xcexcF, is used for the compensation of LDO 100.
When the circuit(s) connected to LDO 100 are not pulling any load current I1160, PMOS pass device 120 has to be completely turned off. This requires NMOS source follower 115 in the output stage to drive the gate voltage of PMOS pass device 120 very close to the upper rail voltage at node 125 in order to reduce the Vgst of PMOS pass device 120. Under certain process comers, where NMOS devices are weak, NMOS source follower 115 might not be able to drive the gate of PMOS pass device 120 to a high enough voltage. When this happens, PMOS pass device 120 is in the subthreshold region. Because PMOS pass device 120 is large, it can conduct significant amounts of current I1160. This current I1160 will cause a charge to build up in C1140. This will cause node 135 to start charging towards the upper rail voltage at node 125. The circuitry connected to node 135 will be exposed to this higher voltage. This condition is not acceptable because the maximum voltage ratings in the circuits connected to node 135 might be exceeded. To prevent PMOS pass device 120 from conducting, the Vgst of NMOS source follower 115 needs to be lowered to enable it to reach a high enough voltage to completely turn off PMOS pass device 120.
Prior art has attempted to resolve this problem in various ways. One method is to decrease the feedback resistance of feedback resistors 150 in order to increase the current that feedback resistors 150 pull from PMOS pass device 120 during the no load condition. This makes the required output voltage swing smaller for NMOS source follower 115 because PMOS pass device 120 is operating under a higher Vgs at the no load condition. But, since PMOS pass device 120 is in the subthreshold region, it follows an exponential current versus Vgs relation. This implies that to obtain a small amount of Vgs change, a large amount of current is needed. Therefore, the no load quiescent current of the regulator would increase substantially.
A second prior art approach is to maintain a constant current source connected to the output, node 135, of PMOS pass device 120. FIG. 2 diagrammatically illustrates a PMOS LDO 200 implementing this approach. Input stage 210 and cascoded device 215 drive the gate of NMOS source follower 115. Both the source and backgate of NMOS source follower 115 are tied to node 117. Node 117 is also tied to the gate of PMOS pass device 120. The drain of NMOS source follower 115 and both the source and backgate of PMOS pass device 120 are tied to the upper rail voltage at node 125. Capacitor 140 (C1) is tied from node 135 to ground. Constant current source 220 is tied across C1140. Under the no load condition, constant current source 220 will discharge the leakage current of PMOS pass device 120. But it will also eventually discharge C1140, causing the output voltage to slowly decay.
Another prior art solution increases the Vt of PMOS pass device 120 by connecting it to a higher potential than the upper rail potential at node 125. This causes the Vt of PMOS pass device 120 to increase due to the body effect. By increasing the Vt, PMOS pass device 120 leakage is eliminated, preventing the output from drifting up. However, to obtain the higher voltage required for the backgate, a charge pump circuit must be used. FIG. 3 diagrammatically illustrates a PMOS LDO 300 implementing this approach. Input stage 210 and cascoded device 215 drive the gate of NMOS source follower 115. Both the source and backgate of NMOS source follower 115 are tied to node 117. Node 117 is also tied to the gate of PMOS pass device 120. The drain of NMOS source follower 115 and the source of PMOS pass device 120 are tied to the upper rail voltage at node 125. Capacitor 140 (C1) is tied from the drain of PMOS pass device 120 to ground. The backgate of PMOS pass device 120 is coupled to the output of charge pump 330. The input of charge pump 330 is tied to the upper rail voltage at node 125. This circuit requires a capacitor for each of its stages, thereby consuming a great deal of die area. Furthermore, this prior art solution introduces additional noise because it switches at a fixed frequency. In order to avoid operating charge pump 330 at the regulator""s bandwidth, it must operate at a higher frequency, resulting in increased power consumption because the power in charge pump 330 varies linearly with the frequency.
An additional prior art approach is the use of rail to rail common source output stages. This approach, however, does not provide the needed low impedance. This, in turn, degrades the power supply rejection ratio (PSRR) because of the bandwidth reduction.
It is therefore desirable to provide a solution that maintains a constant voltage and a low impedance and does not sacrifice significant amounts of quiescent current or die area. It is also desirable that no additional source of noise be introduced or increased power consumption occur. The present invention provides this by connecting the buffer backgate to the upper rail potential during the no load current condition, thereby changing the threshold voltage of the buffer.